The present invention is generally related to integrated circuits (ICs) and, more particularly, to synchronizing data across two clock domains.
Data synchronizers are known and are used to synchronize data moving from one clock frequency domain to another clock frequency domain. For example, data synchronizers are known to synchronize data moving from a higher clock frequency domain to a lower clock frequency domain, and vice versa.
Generally, current synchronization of signals across two clock domains is accomplished using two synchronizers that are tied together in a back-to-back configuration with a buffer connected to the output of one synchronizer and to the input of the other synchronizer. In this configuration, the buffer prevents or lessens the number of hold time violations. The synchronizers may have a relatively large distance between them in the IC layout and/or may have their clocks tied to different trunks, which can result in a low clock skew tolerance. Also, the buffer located between the synchronizers and the metal routing that connects the buffer to the synchronizers both contribute to the overall delay in synchronizing data across clock domains and consume area on the IC. All of these factors tend to reduce the resolution time of the synchronizer logic (i.e., the amount of time allotted for the logic to resolve to a logic 1 or a logic 0), which limits the performance of the IC.
When generating the IC layout with a tool, for example, the two associated synchronizers may be placed by the tool at any location in the IC layout. Thus, there may be a great distance between the synchronizers, regardless of whether they are placed in the same block of combinational logic or in different blocks. Of course, the greater the distance between the synchronizers, the greater the delay in synchronization. Also, because the synchronizers each may utilize a different clock trunk or route, the distance between the synchronizers will typically decrease the clock skew tolerance. Even if the synchronizers are placed in the same block, the utilization of separate clock trunks or routes for each synchronizer can reduce the clock skew tolerance. Also, even though the synchronizers may be placed very close together, it is difficult to ensure that the clock skew will be small enough to enable the buffer to be eliminated.
Accordingly, a need exists for a method and apparatus for data synchronization that minimizes the significance of clock skew tolerance margins such that the possibility that a metastable state will occur is minimized, the amount of time allowed for resolution is increased, and the need for a buffer between the synchronizers and the associated metal routing needed to connect the buffers to the synchronizers is eliminated.
The present invention provides a data synchronization cell that comprises at least a first and second synchronizer that are generally adjacent one another in side-by-side configuration and that have their respective M1/S1 clock ports tied together. The result of this configuration is that the synchronizers are driven by the same clock signal, and the clock signal arrives substantially simultaneously at the M1/S1 clock ports of the synchronizers due to the fact that the synchronizers are side-by-side. This eliminates clock skew or makes it negligible, which allows the buffer to be removed, which, in turn, allows more time for resolution.
In known synchronization cells, a buffer is placed between the data output port of the first synchronizer and the data input port of the second synchronizer to solve clock skew problems and to prevent hold time violations. In such systems, the synchronizers are referred to as being in a back-to-back configuration. The synchronizers may have great distances between them and/or receive their clock signals from different trunks. All of these features of the known synchronizer configurations decrease the amount of time allowed for resolution and increase the amount of area required to instantiate synchronization cells.
Because the synchronizers of the present invention are adjacent one another and have their respective M1/S1 clock lines tied together, clock skew is negligible and thus no buffer is needed between the synchronizers, which increases the amount of time allowed for resolution, reduces or eliminates the possibility of hold time violations occurring, and reduces the amount of area required to instantiate the synchronization cell.
These and other features and advantages will become apparent from the following description, drawings and claims.